This invention relates to controlling time delay.
Time delays (also called skew) occur, for example, in the propagation of clock signals to different parts of a synchronous computer system, impacting the ability to maintain synchronicity. With higher processor speeds (shorter clock cycles), the relative effect of skew increases.
One way to maintain synchronicity uses a phase locked loop (PLL) that has an internal clock in the form of a voltage controlled oscillator (VCO). A PLL receives an input signal (e.g., a reference clock signal that embodies the system clock period (T)), synchronizes the PLL""s internal clock with the input signal""s phase and frequency, and delivers an output clock signal equal to a multiple of the input signal. The PLL may accomplish this synchronicity by controlling a voltage bias to the VCO including a delay line.
As shown in FIG. 1, a delay line 10 may include differential current starved delay stages 12a-k, where k is a number that is large enough to guarantee that the delay through the delay line 10 can be adjusted to a percentage of T, e.g., 2T and T/5, in spite of the effects of any manufacturing process variations, operating temperatures, supply conditions, and range of operating clock periods. The desired time delay may be adjusted to a multiple of T in a number of ways, e.g., by changing the value of k, by dynamically adjusting the current/voltage driving the delay line 10 during circuit operation as described below, or by manufacturing calibration or trim techniques. These adjustment techniques all require using large-range control structures to cover large variability in necessary delay time.
A current digital-to-analog-converter (IDAC) 14 may drive the current/voltage used by the delay stages 12a-k at a node 18. The current/voltage on the control line 18 is inversely proportional to T and to the time delay across each delay stage 12a-k. The IDAC 14 can provide many coarse current steps so that the delay line 10 can be adjusted to the desired delay value as described above. The IDAC 14 also can provide many fine current steps to compensate for the linear relationship between digital inputs 16a-n and the current/voltage at the node 18.
FIG. 2 shows another IDAC 11. The IDAC 11 includes m digital inputs 13, each digital input corresponding to a transistor 15a-m and a switch 17a-m.